The present invention relates to electronic apparatus for selectively and cyclically driving a group of driven elements such as a row of light-emitting diodes employed in an electrophotographic printer, a row of resistive heating elements employed in a thermal printer, or an array of display elements employed in a display device.
In the following description, the driven elements will be light-emitting diodes or LEDs employed in an electrophotographic printer.
In a conventional electrophotographic printer, for example, an electrically charged photosensitive drum is selectively illuminated, responsive to the data to be printed, to form a latent electrostatic image, which is developed by application of toner particles to form a toner image. The toner Image is then transferred to paper and fused onto the paper.
FIG. 46 is a block diagram of the control circuitry of a conventional electrophotographic printer. FIG. 47 is a timing diagram illustrating the operation of the conventional electrophotographic printer.
The printing control unit 1 in FIG. 46 comprises a microprocessor, read-only memory (ROM), random-access memory (RAM), input-output ports, timers, and other elements disposed in the printing engine of the printer. The printing control unit 1 receives a control signal SG1 and a dot data signal SG2 from a higher-order controller, and controls the printing operations performed by the printing engine. The dot data signal SG2 is a one-dimensional digital signal representing a two-dimensional bit map of picture elements (pixels), referred to below as dots.
Upon receiving a print command via control signal SG1, the printing control unit 1 first checks a temperature sensor 23 to determine whether the fuser 22 is within the necessary temperature range. If the fuser 22 is not within the necessary temperature range, the printing control unit 1 activates a heater 22a built into the fuser 22. When the fuser 22 reaches the necessary temperature, the printing control unit 1 activates a driver 2 that drives a stepping motor or pulse motor (PM) 3 used in the developing and transfer process, and activates a charge signal SGC that switches on a high-voltage power source 25 that charges toner particles in a developer unit 27.
The presence or absence of paper and the size of the paper are detected by a paper sensor 8 and size sensor 9. If paper is present, the printing control unit 1 activates a driver 4 that drives another pulse motor (PM) 5. This motor is first driven in reverse by a certain amount, until paper is detected by a pick-up sensor 6, then driven forward to feed the paper into the printing engine.
When the paper has been fed to the necessary position, the printing control unit 1 sends timing signals SG3 (including horizontal and vertical synchronization signals) to the higher-order controller, and begins receiving the dot data signal SG2, which the higher-order controller generates on a page-at-a time basis. The dot data signal SG2 is supplied as a data signal HD-DATA to an LED head 19 comprising a row of LEDs, with one LED per dot. The transfer of dot data into the LED head 19 is synchronized with a clock signal (HD-CLK). The dot data will be referred to below as driving data, since they determine whether each LED is driven or not.
After sufficient driving data (HD-DATA) for one horizontal dot line have been transferred into the LED head 19, the printing control unit 1 sends the LED head 19 a load signal (HD-LOAD), causing the driving data to be latched in the LED head 19. The LED head 19 can then print this line while receiving driving data for the next line.
The LED head 19 prints the line by illuminating a photosensitive drum (not visible) which has been precharged to a negative electrical potential. The potential level of illuminated dots rises, creating a latent dot image. The toner in the developer unit 27 is also charged to a negative potential, so toner particles are electrostatically attracted to the illuminated dots, creating a toner image.
The LEDs are turned on and off in synchronization with a strobe signal (HD-STB-N). FIG. 47 illustrates the timing of this signal and other signals mentioned above. The SG3 pulses shown at the top of FIG. 47 are horizontal synchronization pulses. FIG. 47 illustrates three successive line-printing cycles, for printing lines N-1, N, and N+1 (where N is an arbitrary integer).
Referring again to FIG. 46, to transfer the toner image to the paper, the printing control unit 1 activates a transfer signal SG4 that turns on a high-voltage power source 26, generating a high positive voltage in a transfer unit 28. As the paper travels through a narrow gap between the photosensitive drum and transfer unit 28, the toner image is transferred by electrostatic attraction to the paper.
The paper with the toner image is then transported to the fuser 22, which has been heated by the heater 22a. The heat fuses the toner to the paper, which then passes an exit sensor 7 and is ejected from the printer.
The printing control unit 1 controls these operations so that the high-voltage power source 26 is switched off except while the paper is traveling past the transfer unit 28, as detected by sensors 6 and 9. When the paper passes the exit sensor 7, the printing control unit 1 also switches off the high-voltage power source 25 of the developer unit 27, and stops the pulse motor (PM) 3 used in the developing and transfer process.
The above sequence is repeated for each page.
FIG. 48 shows the structure of the conventional LED head 19 in more detail. The driving data HD-DATA and clock signal HD-CLK are provided to a shift register comprising, for example, two thousand four hundred ninety-six flip-flop circuits FF.sub.1, FF.sub.2, . . . , FF.sub.2496 (this number of flip-flop circuits is appropriate for printing on A4-size paper at three hundred dots per inch). When two thousand four hundred ninety-six bits of driving data have been clocked into this shift register, the load signal HD-LOAD is activated, causing the bits to be stored in latches LT.sub.1, LT.sub.2, . . . , LT.sub.2496. When the strobe signal HD-STB-N is driven low, bits set to the high logic level (one) turn on light-emitting diodes LD.sub.1, LD.sub.2, . . . , LD.sub.2496 by way of an inverter G.sub.0, NAND gates G.sub.1, G.sub.2, . . . , G.sub.2496, and p-channel metal-oxide-semiconductor (MOS) transistors Tr.sub.1, Tr.sub.2, . . . , Tr.sub.2496. The symbol V.sub.DD represents a power-supply potential.
In a printer employing the LED head in FIG. 48, all of the light-emitting diodes LD.sub.1, LD.sub.2, . . . , LD.sub.2496 that are switched on are switched on for the same length of time, determined by the strobe signal HD-STB-N. Thus if these light-emitting diodes, or the transistors Tr.sub.1, Tr.sub.2, . . . , Tr.sub.2496, do not have perfectly uniform electrical properties, the dots will be unevenly illuminated. This will lead to differences in the sizes of the electrostatic dots in the latent image formed on the photosensitive drum, hence to differences in the sizes of the dots printed on the page.
Although different dot sizes are not readily noticeable on pages containing only line art or text, when photographs or similar types of images are printed, variations in dot size create density differences that can degrade the printing quality to an undesirable degree.
Typical differences in LED output are illustrated by the graph in FIG. 49. Dot position is indicated on the horizontal axis, and optical power on the vertical axis. The light-emitting diodes are disposed in a plurality of semiconductor chips, more specifically LED array chips CHP1 to CHP26, which are driven by a like plurality of integrated driver circuits (driver ICs) DRV1 to DRV26, as illustrated at the top of FIG. 49. Ninety-six light-emitting diodes are integrated onto each LED array chip. The LED array chips and driver ICs are interconnected by wire bonding. The driver ICs are cascaded to form a single shift register for receiving the driving data signal HD-DATA.
The horizontal dotted lines indicate the ranges of variability of the optical power output by the light-emitting diodes in each individual LED array. The horizontal dot-dash lines indicate the range of variability of the average optical output power of each LED array. Thus the dotted lines indicate ranges of dot-to-dot variation within each array, while the dot-dash lines indicate the range of chip-to-chip variation.
As illustrated in FIG. 49, the range of chip-to-chip variation is much greater than the range of dot-to-dot variation within any one chip. One conventional practice has therefore been to grade the driver IC chips and LED array chips according to their average output power, and assemble each LED head from chips of the same grade. Alternatively, the average current that must be supplied to each LED array chip to obtain a nominal average optical output can be calculated from measurements of the LED array chips, the average current supplied by each driver IC can be measured, the driver IC chips can be graded according to their average current output, and each LED array chip can be paired with a driver IC that supplies substantially the right amount of average current. In this way it is possible to reduce chip-to-chip differences, but the dot-to-dot differences within each chip remain uncorrected.
FIG. 50 illustrates another conventional LED head, disclosed in Japanese Patent Application Kokai Publication No. 160659/1989. The first dot section of this LED head comprises an inverter 30-1, four transistors 31-1, 32-1, 33-1, and 34-1 coupled in parallel, three NAND gates 35-1, 36-1, 37-1, a light-emitting diode 38-1, three D-type flip-flop circuits 39-1, 40-1, and 41-1 for storing LED compensation data, and an AND gate 42-1. Other dot sections are similar; the letter N denotes the total number of dots printed by the head.
A strobe generator 43 outputs a strobe signal to the AND gates 42-1 to 42-N. A shift register 44 stores the driving data. The input terminals are an LED power supply terminal 45, a compensation data input terminal 46, a clock input terminal 47, a driving data input terminal 48, and another clock input terminal 49. Flip-flops 39-1, 40-1, 41-1, . . . , 39-N, 40-N, 41-N are interconnected to form a shift register receiving data from compensation data input terminal 46 and clock signals from clock input terminal 47.
When LED 38-1 is driven, for example, transistor 31-1 is turned on responsive to the driving data output from terminal Q1 of shift register 44, while transistors 32-1, 33-1, and 34-1 are turned on responsive to both the driving data from terminal Q1 and the compensation data stored in flip-flop circuits 39-1, 40-1, and 41-1. Transistor 31-1 supplies the main driving current; transistors 32-1, 33-1, and 34-1 supply additional compensating current.
FIG. 51 shows an example of the circuit configuration of one of the flip-flop circuits 39-1, 40-1, 41-1, . . . , 39-N, 40-N, 41-N that store LED compensation data. The typical flip-flop circuit 51 shown in FIG. 51 has data (D) and clock (C) input terminals and a data output terminal (Q). The flip-flop circuit comprises four transmission gates 52, 53, 54, and 55, and six inverters 56, 57, 58, 59, 60, and 61. Each transmission gate comprises a p-channel MOS transistor and an n-channel MOS transistor coupled in parallel. Each inverter comprises a p-channel MOS transistor and an n-channel MOS transistor coupled in series. The total number of transistors in the flip-flop circuit 51 is thus twenty.
The LED head illustrated in FIGS. 50 and 51 can minimize both chip-to-chip differences and dot-to-dot (LED-to-LED) differences, but the flip-flop circuits 39-1, 40-1, 41-1, . . . , 39-N, 40-N, 41-N that store LED compensation data greatly increase the size and complexity of the driver ICs. These flip-flop circuits require sixty (3.times.20) extra transistors per LED, not to mention the two extra input terminals 46 and 47. Extra circuit elements are also required to drive each LED through four transistors instead of just one.
Moreover, the three extra flip-flop circuits store only three bits of compensation diode, allowing only eight levels of adjustment of the optical output. If the step size is 2%, the eight levels are, for example, -6%, -4%, -2%, -0%, +2%, +4%, +6%, and +8%, so adjustment is possible only within the limited range from -6% to +8%. This range may provide adequate compensation for dot-to-dot variations within the same LED array chip, but does not in general provide adequate compensation for chip-to-chip differences.